How much Amperage is compromised by a 4mV drop.


I See Electromagnetic Fields!

This link has schematics of low-side NMOS and high-side PMOS switch:

Further down this link is a schematic of NMOS high-side switch with a gate-driver IC. The gate needs to go about 10V above the drain so you need some voltage source or a boost circuit/chip to do that. Oh, and you can't violate Vgs while doing that either. If you hold the gate high when the source goes too far down it'll blow the gate oxide. In your battery side application with 10 to 15V battery and FET Vgs spec of 20V you won't need to be so careful. Just don't hold the gate and 25V and pull the source down to zero. Probably a resistor gate pullup and zener clamp to source would be best.



Solar Enthusiast
Many thanks for this.
Would go through and check how its implemented, this may be the only way to go - else how would one drive nested NPN Mosfets?
Doesn't seem possible with linear logic.

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