Many people have not, so it was a public service for those who don't understand the complexities of laying down parts on thermally engineered PWBs.
Yea of course
There's a lot of thinking about a lot of things you don't realize just reading this thread if you've never done that kind of stuff before. You need to think about your constraints but also some other things like larger scale manufacturing because if you use supra custom parts or a million assembly steps then it'll not scale well... For example I've done everything to avoid the cut corner on the busbar but I couldn't (well, I could but it would mean a longer PCB just for that... compromises...).
And that's not even an aluminium core PCB, you can go really deep really quickly in the rabbit hole ^^
Trying to understand the gate drive. You have two sets of 10 parallel fets. Shouldn’t the two sets have separate drive circuits. Right now you have the two driver outputs connected together, going to all 20 fets.
Have you done an analysis that driver current of 6A is adequate to turn on 10 fets?
So the design is maybe a bit unusual for two reasons: having enough gate current and redundancy.
The problem isn't really turning on the mosfets, it can take hundreds of µs I don't really care, it's turning them off fast. The faster I turn them off and the less the current has time to rise in case of a short circuit and that means less energy stored in the inductances of the circuit (mainly wires inductance) so less energy to dissipate.
The actual turn-off time just for the FETs is a hair less then 300 ns worst case and once you add the various delays of the full chain it comes to a bit less than 4.5 µs worst case. But I'll actually replace the op-amp for the current sense because I want more accuracy and so I'll try to find a faster op-amp while I'm at it, I may be able to shave 1 µs of the total.
So I needed two drivers to have enough gate current to turn them off fast enough. And then I saw that by connecting the two drivers outputs together I could add redundancy at the cost of only a trace and a few more resistors (bad idea to connect the outputs directly and also bad idea to not have one resistor per gate). And it has the side benefit of ensuring all the mosfets turn on and off at the same time, otherwise one half could be delayed relative to the other.
Do you know the thermal resistance of circuit board to ambient for the power fets?
I could do a simulation or calculations but I was more interested in the thermal resistance with a heatsink on the back (BTW much harder to find papers about that than for just a PCB to ambient). The PCB should add less than 4 °C/W which is low enough as I have 2.2 W worst case to dissipate per mosfet at 300 A so the PCB will add less than about 10 °C to the Tj at that power level.
I want to be able to handle 50 °C ambient, ideally 55 °C. I'll will see what heatsink size I really need after doing some real life tests. I designed with some margin at each step so I should be able to have pretty small heatsinks (still need to do the their outlines like for the busbars now I think about it...), with any luck they'll not even go past the board. I could also derate a bit like for example 300 A at 30 °C, 280 at 40 °C and 260 at 50 °C but I don't want to do that.
One of the reasons I choose the Chargery BMS is that it doesn’t have fet disconnects. I don’t want a 200A fet disconnect. I can disconnect the Inverter with a low current command.
Well, I don't trust whatever shutdown electronic they use in the inverter as it hasn't been made for emergency shutt-off but ony for a remote on/off switch. Also, doing that only protects against the inverter over-discharging the battery, it doesn't protects agaisnt anything else like short-circuits and it doesn't shut off the others loads. But all that is a personal choice of course