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DIY BMS design and reflection

The INA226 can be purchased as finished modules:
I would just modify them, desolder the shunt, solder a voltage divisor instead, solder the address bridges.
Then, all modules can be wired in parallel vertically, bus-wise, you don't even need a PCB.
For a 24V LiFePo with 8 cells, you would need 8 cell INA226 modules, plus one -unmodified, for the current and the total voltage.
Together with an ESP8266, the whole BOM will be under 20€.
x2 if you need 48V...
 
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That should do a good job of sinking heat out of that area.

It's more for shielding and having a low inductance ground than for thermal reasons, but yea, some thermal conductivity is always welcome on that kind of temperature sensitive circuitry ;)


Are you still on the Nano?
An ESP8266 with IIC DAC and eventually IIC IO extenders would be much more adapted to do the job.
It provides natively a WiFi connection, so you don't need to retrofit a networking.
It provides much more RAM/ROM speed and power.
It can be programmed with the Arduino IDE and even provides On The Air reprogramming..

I don't want WiFi (or any wireless com actually) because of two main reasons: reliability and security. That's why I chose ethernet (well, that and the nice features of TCP/IP like the advanced adressing and built-in error correction).

WiFi isn't reliable, especially as my house has reinforced concrete floors and hollow bricks for all the walls, and spans two floors + the basement. Plus I plan to have a lot of other things on that network so I highly doubt a WiFi router will be happy with dozens of nodes.

It's also higly unsecure, basically all important stuff in my house will communicate on that network, I don't want anything wireless for that.

RAM/ROM should be enough, that's also why I chose the Every version of the Nano which has additional RAM and FLASH.

I don't use (that piece of crap that is) the arduino IDE, it can't even handle sub-directories properly. Thanks to that and other things we have people putting all the code in one .ino file which is thousands of lines long of unreadable code. So yea, being able to use the arduino IDE isn't a requirement at all for me.

So I'll maybe use something else than the Nano for a 4s version which is more mobile intented and would be 100 % everyone needs oriented (the current version is still a personal project first that I try to open and adapt as much as possible to fill everyone's needs) ;)

You're still free to not use the ethernet module and then you now have a SPI port to do whatever you want to with it (only constraint is that it's shared with the ADC), you can use it as-is, or add a BT or WiFi module, or bit-bang you own protocol (I2C, RS485, CAN, totally custom, ...).


You have got chips like the INA226 that provide an off-rail "current" measurement up to 40V potential difference and an IIC interface with up to 16 addresses. It provides a very precise factory calibrated 14bit DAC.
However, the "current" measurement is -as always- basically a differential 75 millivolts measurement around a shunt.
If you replace the shunt by a simple voltage divider, you can build a measurement ladder for the voltage of every cell up to, say, +24V battery pack,
So you basically have 6 INA226 to measure the voltage of the cells + one to measure the current for each 24V subpart.
You could even built a 2P/6S BMS with 12+2 INA226 on one microprocessor
It is easy to scale: for 48V or more P, you just use two units, and there is no upper limit.

Well at 2.5 USD in 10 quantities that's 40 USD just for the INA and you still need to add all the support components to that. That's far too expensive, and even more so as it would be far less accurate than my solution. It's also in a PITA package and would take a lot of PCB real estate. And it's power hungry and uses the PITA I2C com.

I like the INA226 for things like what it's meant to do as it does it well and is simpler than having a discrete op-amp with a discrete ADC and Vref, but here it's not well suited at all.


If the microprocessors are ESP8266, you will communicate/programm over WiFi and be completely galvanically separated, so you will not get any potential difference problem.

Ethernet is fully galvanically isolated so no problem here.


The presentation of the information could be done in the cloud, so you just need no hardware.

Define "in the cloud" in this context please.

Also if it means internet connected then no, again, security means air-gapped from internet connected networks. When I see industrial plants control panels indexed by google I can tell you it's a (very (super)) bad idea to connect that kind of devices to internet.


The solution with one INA per cell (plus one for the current) is the most accurate and the fastest, but not the only one:

Actually no, the INA is far less accurate (tempco of 10 µV/°C vs 0.3 µV/°C, gain error of 0.1 % vs 0.01 %, ...).


Indeed, we can do it much simpler, cheaper and easier:
We just use the fact that we have a ladder of power cells to wire a comparator between every pair of cells.
We don't need to be fast, if we check the cells at night, with no load or a constant load the voltage wouldn't change that fast.
After the first sweep, we have the approximate voltages, so the next measuring cycles will be just around the the last known cell values.
That could be done much faster.

The bottom high-voltage op-amp will provide a voltage reference from 0v to Vcc depending on the PWM output and the value of R10.
With an ESP8266, you can provide 1024 steps of PWM.

The schematic shows the first 4 cells; you can replicate the top with additional comparators, until you have all the cells you need.

The voltage at A0 will make a clear step each time the comparison voltage will exceed the battery voltage of the next cell, so you can get the voltage of every cell upon one iteration. There is no need to do a multiplex, nor to use a lot of exotics chips...
and you do all the stuff with two I/O pins only...

Well that's one op-amp per cell + a few support op-amps so I don't see how it's simpler, cheaper and easier than having 2 MUX and 3 op-amps for 16 cells.

It also adds a big error term because of the diodes on the output of the op-amps (you basically add a temperature sensor in series with the signal...). And I can't see how it would work as the op-amps are in open loop mode.

Also PWM in a sensitive analog measurement circuitry? that's the last thing I want. And 1024 steps is not good enough so you would need an additional DAC.

But thanks for the ideas, it's always interesting to see other solutions to a problem ;)


Edit: well, you totally changed your last post so I'll answer to it again:

The INA226 can be purchased as finished modules:
I would just modify them, desolder the shunt, solder a voltage divisor instead, solder the address bridges.
Then, all modules can be wired in parallel vertically, bus-wise, you don't even need a PCB.
For a 24V LiFePo with 8 cells, you would need 8 cell INA226 modules, plus one -unmodified, for the current and the total voltage.
Together with an ESP8266, the whole BOM will be under 20€.
x2 if you need 48V...

I'll not buy components from aliexpress for this project. They're almost all factory rejects or fake copies not meeting the original specs in either case.

So that's 40 € for just the cell voltages and current measurement on a 16s pack, with fake components and no scalable manufacturing (desoldering chips isn't realistic beyond a few units). I'm at around 30 € with my current solution, with top tier components and proper manufacturing method, and at least an order of magnitude better accuracy ?

I already spent hundreds (actually I'm pretty sure I'm over a thousand at this point) of hours on the design, component selection, etc... optimizing everything I could, so it'll be hard to do better (I wish a magical better and cheaper solution would exist, but yeah, not gonna happen... ?).
 
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Yes, but only right or wrong for my use case of course, you can have a totally different opinion and that's fine ;)

Also I don't say that without reasons (reasons you conveniently avoided quoting BTW) because there's no point just in saying "X is wrong" without explaining why.

You proposed some alternative solutions (which is always welcome BTW, I thank you for that ;)) but they don't meet the requirement and/or are not better and/or less expensive than the current solution I use so why would I chose it?

I discarded a lot of other solutions in the initial design process, heck I even just changed the topology from op-amps --> MUX to MUX --> op-amp because it's better and cheaper. If one of your solutions would be better I would already be implementing it, trust me.
 
Yes, but only right or wrong for my use
I've been watching this thread from post 1. I know absolutely nothing about the design and engineering of these types of projects, but your attention to detail and your willingness to share and consider and/or implement external input is well documented. When you get it done, I am a buyer....provided I live that long:cool:
 
Oh, for me it's just because I could have it all running within a week without need to design a PCB.
I found the INA226s to be all precise enough and match my meters up to the 3rd digit out of the box.
I am just tinkering in my corner and do not have requirements like for nuclear power plants.
I really would not care if my measures would have an error of 1mV on the temperature range from -40°C to +60°C...
I'll concentrate on my MPPT improvement now.
 
I've finished routing U230 and I routed U130 + U340, and re-routed U240 who was on the back side, plus improved the routing of some power traces:

pcb.png

So now I'll go back to the schematic to add a few missing things around U150 before I re-route U140, U150 and U160. Hopefully it'll be a lot cleaner than the current mess on the bottom left and bottom center.

And I was able to squeeze a 6 pins connector to breakout the SPI port for those who don't want to use the ethernet module:

pcb_details.png
 
Today I made all the last changes I wanted to make on the schematic (replace the 0.1 % resistors with 0.05 % ones and add the shunt voltage selection jumpers and resistors).

I also had time to route U150 (still need to do U140 and U160):

pcb.png

As you can see I now have nice ground planes under all the sensitive circuits which is a lot better than before for signal integrity and decoupling ?

More details:

pcb_details.png

The BMS can now handle 50, 75 and 100 mV shunts easily :)
 

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I finished routing everything ?

pcb.png

I also cleaned a few traces and replaced the big ground traces on the bottom and bottom left by a ground plane.

More details around U140 and U160:

pcb_details.png


Some 3D views:

pcb_3d_front.png

pcb_3d_back.png
 
So I also have a few changes to make on the HWPB. Not really complex or hard ones but time consuming because I need to re-calculate some dividers which is a PITA because of the positive feeback of the comparators.

Today I started to make the changes not related to the dividers (mainly I removed the Vref buffer because it was useless besides potentially adding some offset which isn't good, and adding the missing label for the Vaux connector) but there isn't much to show yet so I'll wait to have done more to post the udpated schematic and PCB captures.

I also updated the power spreadsheet; the much better but also more power hungry OPA2189's added around 100 mW to the total. Keep in mind all numbers are the absolute worst case, typical values will be around half that, or even less.
 

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So... after dozens of voltage dividers ratios calculations I changed almost all of them. Main changes are:
- the NMC OVP is now 4.14 V instead of 3.99 V
- discharge OCP short term is now 990 A and the charge one is at 482 A instead of around 430 A for both
- long term ones are now around 310 A instead of 335 A
- battery OTP is now 53 °C and system OT is now 63 °C instead of 58 °C for both
- fire threshold is now 121 °C instead of 116 °C

I also moved the Vref for some of the temperature comparators to the 4 V one (they were on the 2.050 V one) so all comparators now use the 4 V Vref and leave the 2.050 V one alone (which is used for the sensitive measurements) :)

I corrected a big calculation error on the RC networks for the long term OCPs timers (they were way too fast, something like 2 sec instead of 30 sec) and I also moved the caps from the +12 V to GND so it's fail-safe (MLCC caps failure mode is uasually short-circuit).

I reflected the changes on the PCB too; I still have a few resistors to re-route:

pcb.png

I also want to remove 12 of the 47 k resistors I initially put as input protection but they're not really useful in the end for a lot of reasons. It may not be possible routing-wise tho (I used some resistors as jumpers obviously) so I'll see.
 

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The HWPB is now finished:
Almost.
Are you going to teardrop the traces where they meet pads & vias?

In the photo-realistic images, signal vias appear to have small overlap. Most look like they could be larger.

Did you have design rules from fabs?
I found it difficult to get a good set. Width, space, overlap etc. as a function of thickness and so on.
Sometimes they informed me of the rules after I submitted files. A different interpretation from what they gave me beforehand.
 
I don't understand any of it but it looks beautiful. :)

Thanks ;)


Are you going to teardrop the traces where they meet pads & vias?

In the photo-realistic images, signal vias appear to have small overlap. Most look like they could be larger.

I didn't planned to but still can add some. I already avoided acid traps on traces meeting at 90° or less by adding chamfers (even if with today's fab it shouldn't be a problem anymore...).

The smallest traces are 0.4 mm (15.75 mils) and the smallest vias are 0.4/0.7 mm so they're not super small. The annular dimension is then 0.15 mm (5.90 mils).

The fab capabilities are unclear as I have 2 similar specs: 3 and 5 mils for PTH deviation. Using the 5 mils one that means I can be left with only 0.9 mils of copper if I'm unlucky, so for safety I might add teardrops if it's not too complicated with KiCad.

I just saw their annular ring capability is 6 mils, so... oops... I guess I'll have reduce the drill size to 0.35 mm for the smallest vias as I can't increase the via size without having a million DRC clearances violations with the current PCB... Fortunately they allow holes as small as 0.25 mm so I'm ok.


Did you have design rules from fabs?
I found it difficult to get a good set. Width, space, overlap etc. as a function of thickness and so on.
Sometimes they informed me of the rules after I submitted files. A different interpretation from what they gave me beforehand.

Yes, it would be suicidal to design a PCB without them ^^ You can see them here: https://www.allpcb.com/standard_pcb_manufacturing_capability.html

So far I never had a problem with Allpcb, and their specs are relatively clear and complete for the most part.
 
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I suppose small volume from one vendor is all you need.

When I've grown the dogbone size with larger vias, that "million DRC errors" was a small number, took me 20 minutes to push traces around and fix it.
Larger drill size is preferred, and having enough overlap that wandering drill doesn't break out copper improves yield.

The inside corner where a trace meets pad or via without teardrop can be a point where trace fractures, so reliability improvement as well as yield due to drill tolerance.

My boards had things like 2 oz copper plus plating on the outside for heat spreading and power, so that conflicted with spacing rules for SOIC and other small parts.
Smaller pads were often metal defined rather than soldermask defined, and I couldn't get a rule for distance between soldermask opening and unrelated trace, to ensure it was covered and prevent solder bridge. I don't think I see it in your rules either.

I didn't do a lot of PCB, most circuit/schematic for them, or layout of thin-film MCM. But I did do a handful of board designs for an instrument.
I tried to use as low-tech a PCB fab as possible, but needed to use the performance it could offer, so not just the basic rules for 1/2 oz copper.
Each time the purchasing guys went to a different fab for better price, there was a request to make changes to stackup and also dimensions.
Some assemblers even asked us to approve bakeout conditioning of opened reels of parts that didn't meet instructions in the component data sheets.
 
In the schematic I see resistors in the 100k range, some several meg-ohm.
PCB probably assembled with no-clean flux?
That works OK for low impedance circuits and dry conditions, but can affect accuracy of analog.

We had a board that used 6 meg resistors in a supply voltage sensing "power good" circuit. After a change in weather conditions, it wouldn't turn on. The setting was off 20%, indicating a 30 meg leakage. Cleaning with IPA fixed that. I had meg ohm circuits needing better than 0.1% stability, which depended on PCB resistance (10 Gohm), couldn't work with such leakage either. For a future design I would put interdigitated patterns on the surface allowing hi-pot or megger testing of assembled boards to check surface resistivity.

Give them a good soak and cleaning in IPA, then thoroughly dry so all water is gone.
Conformal coating would be a good idea too.
 
I suppose small volume from one vendor is all you need.

I don't think I'll have the need to go higher than a few hundreds so, yes, not big volumes.


When I've grown the dogbone size with larger vias, that "million DRC errors" was a small number, took me 20 minutes to push traces around and fix it.
Larger drill size is preferred, and having enough overlap that wandering drill doesn't break out copper improves yield.

The inside corner where a trace meets pad or via without teardrop can be a point where trace fractures, so reliability improvement as well as yield due to drill tolerance.

Yep ;) I just need to see how easy/hard it'll be to teardrop the vias/pads (short version: KiCad is weird...).


My boards had things like 2 oz copper plus plating on the outside for heat spreading and power, so that conflicted with spacing rules for SOIC and other small parts.
Smaller pads were often metal defined rather than soldermask defined, and I couldn't get a rule for distance between soldermask opening and unrelated trace, to ensure it was covered and prevent solder bridge. I don't think I see it in your rules either.

Pretty sure KiCad don't have such rule either. I checked the minimal fab capability about solder mask bridges and I'm far above, even on the DPB which is the tricky one because of the thermal design and voltage clearances needed. Other boards have SOICs or bigger (excepted a few TSSOP on the BMSB because bigger packages weren't available) so no problem on the bridges.


I didn't do a lot of PCB, most circuit/schematic for them, or layout of thin-film MCM. But I did do a handful of board designs for an instrument.
I tried to use as low-tech a PCB fab as possible, but needed to use the performance it could offer, so not just the basic rules for 1/2 oz copper.
Each time the purchasing guys went to a different fab for better price, there was a request to make changes to stackup and also dimensions.
Some assemblers even asked us to approve bakeout conditioning of opened reels of parts that didn't meet instructions in the component data sheets.

That sounds sketchy... ?


In the schematic I see resistors in the 100k range, some several meg-ohm.
PCB probably assembled with no-clean flux?
That works OK for low impedance circuits and dry conditions, but can affect accuracy of analog.

You're absolutely right. Everything critical is 100 k or less. Most of the higher value resistors are for the comparators positive feedback, so leakage would change the threshold voltages a bit but nothing too big. The other ones are used to tune reference voltages and threshold voltages but are in // with lower value ones, so not a big problem either.

However, I'll obviously not count on luck and I already planned to clean the boards with IPA.


We had a board that used 6 meg resistors in a supply voltage sensing "power good" circuit. After a change in weather conditions, it wouldn't turn on. The setting was off 20%, indicating a 30 meg leakage. Cleaning with IPA fixed that. I had meg ohm circuits needing better than 0.1% stability, which depended on PCB resistance (10 Gohm), couldn't work with such leakage either. For a future design I would put interdigitated patterns on the surface allowing hi-pot or megger testing of assembled boards to check surface resistivity.

I'm lucky to "only" want 0.05 % with 100 k (so 200 M) :)


Give them a good soak and cleaning in IPA, then thoroughly dry so all water is gone.
Conformal coating would be a good idea too.

I even have a US cleaner but I'm afraid of degrading some components. I didn't read a lot on that problem yet tho, I just know it can be a problem.

I was actually thinking of having a rugged version with conformal coating, glued connectors and TH components, etc... problem of doing all that is that it increases the cost and most people don't need it so that's why I was thinking of having that as an option. Maybe I'm wrong, I don't know, I'm still in the design stage anyways, I'll get to that question when I'll be there.


BTW: Thanks for your very good remarks, you're very knowledgeable ;)
 
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