Yeah, got it. Source connects to PV ground, which has a lower potential than battery ground. Gate drive comes from PV power. This will work.They aren't at the same potential but they share the same ground which is PV negative.
That has analog inputs too.
You can add a temperature sensor, for instance 10 k ohm NTC thermistor, biased with a pullup resistor and with an optional parallel resistor. Thermally bonded to the heatsink but electrically isolated, this lets you monitor its temperature. Another in the air could also let you monitor ambient temperature. If heatsink exceeds some maximum, turn off the MOSFETs because they're dissipating too much power. Wait until below some lower temperature (hysteresis) before turning back on. I like to do shutdown in hardware but that takes a circuit to do comparison & hysteresis, and you've got a microcontroller. Difference between heatsink and ambient is an indication of how much power.
If you like you can monitor PV voltage (which is only available from charge controller when MOSFETs are turned on.) Put two 100k resistors in series from 5V to GND, connect the midpoint to an analog input. Do that again to a second analog input. Differential voltage is zero, and input impedance of each resistor divider is 50k ohm. Put a 2M ohm resistor (or two, 1M in series) from one to PV positive, the other to PV negative. Each of those is a 41:1 divider, with 2.5V headroom to voltage rails. That will accept input in the range +/-102.5V while keeping Arduino inputs within zero to 5V, and 0.05 mA. Multiply the difference between those two inputs by 41 to get PV voltage.
Don't know about the Arduino boards, but the microcontrollers are rated either 85C or 125C. 85C is good for normal environments, with an enclosure and parts inside that might heat it up. If getting directly sunlight or mounted on/in same enclosure as power devices, best to have the 125C component.
Hi,
here's the draft schematic for 4S Cell balance module.
View attachment 19972
Idea is to monitor voltage of each individual cell ( via voltage divider) and short local electrodes once voltage reaches pre-determined top charge.
While exact algorithm for balancing can be done in microprocessor, dissipating excess charge is regulated via logic level Mosfet which is in series with electrodes of the cell. Since balance current is small ~150mA, I suppose logic level Mosfet should be able to do it without requiring explicit driver config.
Not sure how its done in commercial setups but using the same leads for Voltage monitoring and balancing could creep certain level of error in measurements. This could especially be true when Mosfet is active and Voltage at Positive junction of the voltage divider resistors drops slightly due to the burn load.
Please pour-in you comments/ suggestion if this makes any sense at all.
Regards
That's super complex for nothing. Just use a simple voltage divider made with two resistors. If you want 100 k (PV side) and 10 k (GND side) will give you 11:1 attenuation so you can measure up to 55 V which should be plenty enough, add a second 10 k in parallel of the first one to get a 21:1 ratio and be able to measure up to 105 V if needed
Thanks @BiduleOhm for the critical review.Your balancing circuit will not work as only the mosfet nearest to GND will be able to be turned on by the MCU, the other ones have their source to a potential too high for the 5 V of the MCU to turn them on.
Also your divider network for the cell voltages is not wired correctly, and I'm pretty sure the resistor values are wrong.
Thanks @Hedges - Have picked direct feed from PV panels to monitor voltage across terminals and used 50k pot in similar fashion. Hoping that should work, cant't see why not.He's got MOSFETs that isolated negative side of PV array from charge controller.
So how's your simple voltage divider made with two resistors going to let him measure PV voltage, again?
(I sometimes put two blocking elements in series for higher voltage)
Differential signals, nominally mid-range of the ADC, takes care of any voltage offset, whether PV negative goes to ground or is isolated.
A capacitor should be added from each ADC input to GND, filtering out noise of frequencies higher than your sample rate. Keep it low enough to study peak-search of controller, but attenuate switching noise if present.
PV negative is not connected directly to microcontroller but it latchges to SCC ground when mosfets are activated. SCC is internally hardwired with Battery ground - which is common ground for the microcontroller also.1) PV positive gets divided by potentiometer before going to microcontroller, but not clear to me that PV negative also reaches microcontroller. (That is why described both connected, so you can read two ADC and compute the differential)
Do you think putting a 4.7v zener in parallel with resistance at each ADC input could help save from unwanted spikes/ accidental flashes?Input voltages beyond power/ground rails are often most destructive when device is powered, causes "latchup".
Sufficiently high impedance so injected current stays within spec limits is usually good protection. There are some clamping devices, and with low input current those do their job.
Corrected Mosfet charging mechanism by using optocouplers as drivers which shall utilize charge from PV source for the purpose.
Since now multiple drivers are to fed - beefed up current from Zeeners as well.
For the Voltage divider network, now using 10k potentiometers (Input current ~1mA) since even with a nominal manufacturing tolerances of 5% accuracy could be an issue when detecting 0.001V. Also mapping things with a variable resistor could make-up for any miscalculations and % error in the process - what do you say? or is it better to use combination of fixed and variable resistors to keep feed consistent around 1mA?
For the capacitor part - should 1uF be fine or is it still too big to slow down voltage sensitivity? Unable to calculate capacitance, this one is just a wild guess.
As added protection from unwanted feed from voltage leads reaching microprocessor when its OFF (which could potentially destroy it)- have added an opto switch cutting off the common ground, which would allow feed voltages to reach ADC only when opto is activated on purpose. However now with the small capacitors @ ADC input - could they still not induce the same effect?
1) PV positive gets divided by potentiometer before going to microcontroller, but not clear to me that PV negative also reaches microcontroller. (That is why described both connected, so you can read two ADC and compute the differential)
I am not sure if we can reads less than '0' voltages at microcontroller inputs (In case ground reference of PV is lower than that of microcontroller/battery since its floating) which would easily damage the input pin.
Do you think putting a 4.7v zener in parallel with resistance at each ADC input could help save from unwanted spikes/ accidental flashes?
What other clamping components can be of use here?
Yes Cal, its intentional to activate balancing only during charge cycle.Looks like cells can only be balanced while solar is operational.
True, trying to rearrange things so we just have to deal with one ground for internal circuitry while the other ground comes into picture only during PV charging process.There is a price to pay when using a low side disconnect switch. You’re now dealing with several grounds. This gets messy.
Yes, logically its always better to go with a clearer design but we have following concerns here:Though I’ve been away from designing quite a while, I think a high side disconnect switch is a better way to go. No reason to shy away from P-channel fets.
Now there’s just one common ground.
What do you guys suggest? Is it prudent to abort PV negative isolation plan and go with P-channel mosfets at this stage or we remain on course?
You can still use your N-Channel fets for a high side switch. That’s what BiduleOhm uses in his design.
Resistors are so cheap (on an SMT PCB, where layout and assembly is basically coding, unlike manual breadboards) that I use them a lot. My "super complex" resistor circuits are balanced so they perform stably over temperature and voltage. In most cases I use 0.1% thin-film resistors to maintain 0.1% or better performance over temperature.
Also my main concern would be the 2 M resistors, that's pretty high and I'm pretty sure the MCU input leakage current will skew the measurements far more than any resistor tempco mismatch, etc. Also we're talking about an on-board ADC with only 12 bits and an internal Vref (which is notoriously crappy...) so more like 10 ENOB at best; so 0.1 % will be a single LSB at that point, you would need oversampling to get back to a more accurate measurement.