interesting! thanks for the links to read
regarding AC inverting, it seems 50 Hz or 60 Hz are the most common for gridline stuff
i've dealt with sinusoidal error in time series ADC before by characterizing the error component as sinusoidal by visualizing, finding the frequency, then averaging integer number of cycles to null the partial cycle averaging error
but that time, i used a fixed number of samples, so if the frequency of it changed, error would immediately creep back into the averaged value output
however, it would be nice for user to not need to set 50/60 Hz mode for such a feature to operate
a buffer of say 6 cycles of 60 Hz would be 0.1 second, at 300 Hz sampling, that's only 30 samples to hold in memory
5 cycles of 50 Hz would be 0.1 second, at 300 Hz sampling, 30 samples
to calculate average value, i would maybe go backwards from the start of the buffer of samples and find the local min and max to easily mark the cycle peaks and valleys. then average over a configurable number of AC cycles. this ought to handle 50/60 Hz aliasing decently.
fitting a sinusoid to the same data might provide higher quality output, but it's heavier than minmax cycle detect (at least the algorithm im aware of)
my dream ideal would be that the number of detected cycles to average would be determined or matched by the BMS data refresh rate, e.g. if reporting values at 1 Hz output, keep minimum 1 second of ADC sample buffer and calculate over the entire buffer each time. this ought to remove a lot of error resulting from subsampling
this thread is super neat?
You forgot that the problem isn't to sample a nice 60 Hz sinus, the problem is the waveform is much more complex and has much higher frequency components in it, and they are non-predictable so you can't do that kind of SW adaptative stuff. But, given the highest frequency we want to sample is quite low in this case my guess is an ADC with a few kSps is good enough in conjunction with a proper low-pass anti-aliasing filter (and the price is still reasonable)
